Computer operating systems use virtual memory techniques to permit application programs to address a contiguous working memory space, even when the corresponding physical (machine) memory space is fragmented and may overflow to disk storage. The virtual memory address space is typically divided into pages, and the computer memory management unit (MMU) uses page tables to translate the virtual addresses of the application program into physical addresses. The virtual address range may exceed the amount of actual physical memory, in which case disk storage space is used to save (“swap out”) virtual memory pages that are not currently active. When an application attempts to access a virtual address that is absent from the physical memory, the MMU raises a page fault exception (commonly referred to simply as a “page fault”), which causes the operating system to swap the required page back from the disk into the memory.
Input/output (I/O) devices usually use physical memory addresses in accessing host memory, but some virtual memory addressing techniques for I/O have been developed. For example, the PCI-SIG organization (Beaverton, Oreg.) has developed a set of I/O Virtualization (IOV) specifications. The PCI-SIG Address Translation Services (ATS) specifications, including ATS 1.0 and 1.1, provide a set of transactions for PCI Express components to exchange and use translated addresses in support of native I/O virtualization. These specifications can be used in conjunction with system virtualization technologies to allow multiple operating systems running simultaneously within a single computer to natively share PCI Express® devices.
Welsh et al., in a paper entitled, “Incorporating Memory Management into User-Level Network Interfaces” (Department of Computer Science, Cornell University, Technical Report TR97-1620, Feb. 13, 1997), describe an architecture in which a network interface (NI) performs address translation between physical and virtual address spaces. The paper presents an extension to the U-Net user-level network architecture (U-Net/MM) that allows messages to be transferred directly to and from any part of the address space of an application. This capability is achieved by integrating a translation look-aside buffer into the network interface and coordinating its operation with the virtual memory subsystem of the computer operating system. This mechanism is said to allow network buffer pages to be pinned and unpinned dynamically.
Some virtual memory addressing techniques for I/O have been described in the patent literature. For example, U.S. Pat. No. 6,321,276, whose disclosure is incorporated herein by reference, describes methods and systems for processing I/O requests including virtual memory addresses. A “recoverable I/O request processor” translates virtual memory addresses to physical memory addresses utilizing translation tables local to an I/O device. If a local translation fails, the I/O request processor requests virtual address mapping information from the operating system.
U.S. Patent Application Publication 2004/0221128, whose disclosure is incorporated herein by reference, describes virtual-to-physical memory mapping in network interfaces. A plurality of processing nodes in a network have respective addressable memories and respective network interfaces. Each network interface includes a memory management unit with at least one mapping table for mapping virtual addresses to the physical addresses of the addressable memory of the respective processing node.
U.S. Pat. No. 8,255,475, whose disclosure is incorporated herein by reference, describes an input/output (I/O) device that includes a host interface, for connection to a host device having a memory, and a network interface, which is configured to receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Packet processing hardware is configured to translate the virtual addresses into physical addresses and to perform the I/O operations using the physical addresses.